The invention is related to a method fabricating a semiconductor device with reduced intralayer capacitance between interconnect lines and a resulting semiconductor structure.
Intralayer (or intralevel) capacitance is a major obstacle in achieving higher levels of integration. Higher levels of integration require smaller distances between metal lines with the region between metal lines having correspondingly higher aspect ratios (i.e., the ratio between the gap height and gap width). With the continual improvement in reduction of metallic line widths to the submicron range, interconnect delays become an increasing problem because of parasitic capacitance between the interconnect lines.
Several techniques have been utilized to reduce the dielectric constant between spacings of metal lines. Some proposals utilize interposed inorganic spin-on materials having low dielectric constants as, for example, hydrogen silsesquioxane (HSQ) or fluorinated silicon dioxides. However, these methods are successful only in reducing the dielectric constant to approximately 3.0 and involve complicated and expensive processing steps. Moreover, the resulting dielectric constants are not as low as desired especially with the continual push for higher integration resulting in ever higher aspect ratios.
An alternative method is to utilize an air gap between neighboring metallic lines so as to achieve the dielectric constant of approximately one. A conventional method utilizing an air gap interposed between adjacent metal lines is shown in FIGS. 1-4. Reference is also made to prior U.S. Pat. No. 5,641,712 and the article by J. G. Fleming and E. Roherty-Osmun entitled "Use of Air Gap Structures to Lower Intralevel Capacitance," Feb. 10-11, 1997 DUMIC Conference, both of which documents are incorporated herein by is reference.
FIG. 1 illustrates a portion of an interconnect structure 10 showing a silicon dioxide layer 12, a metalized layer such as aluminum 14, and a patterned photoresist layer 16. The interconnect structure 10 is formed on a semiconductor chip which is part of a semiconductor wafer. The metal layer 14 is etched away to form metal lines 20, 22 and 24, after which the photoresist layer 16 is stripped away with the resulting structure shown in FIG. 2. A dielectric 28 (e.g., SiO2) is now deposited over the structure of FIG. 2 in such a manner as to enclose air gaps 32 and 34 as shown in FIG. 3. The manner of depositing the dielectric layer 28 is known in the art as shown in the aforementioned U.S. Pat. No. 5,641,712 and may include inert ion sputtering and may be done with or without the formation of spacers. After the dielectric layer 28 is deposited a second dielectric layer 38 (e.g., HSQ) is utilized over dielectric layer 28. A second dielectric layer is typically planarized and the process may then be repeated.
While the above-described process is successful in entrapping air gaps between metal lines, the process may not be utilized to create air gaps when a damascene process is used for metalization.